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DATE
2000
IEEE
88views Hardware» more  DATE 2000»
15 years 8 months ago
Techniques for Reducing Read Latency of Core Bus Wrappers
Today’s system-on-a-chip designs consist of many cores. To enable cores to be easily integrated into different systems, many propose creating cores with their internal logic sep...
Roman L. Lysecky, Frank Vahid, Tony Givargis
EUROMICRO
2003
IEEE
15 years 9 months ago
Enforcing a lips Usage Policy for CORBA Components
Software components promise easy reuse, dependability, and simplified development. Problems arise when implicit assumptions about the use of the component are encoded in the imple...
Wayne DePrince Jr., Christine Hofmeister
FPL
2008
Springer
254views Hardware» more  FPL 2008»
15 years 6 months ago
Digital hilbert transformers for FPGA-based phase-locked loops
The phase detector is a main building block in phaselocked loop (PLL) applications. FPGAs permit the realtime implementation of the CORDIC algorithm which offers an efficient solu...
Martin Kumm, M. Shahab Sanjari
ICCAD
2001
IEEE
217views Hardware» more  ICCAD 2001»
16 years 1 months ago
ASF: A Practical Simulation-Based Methodology for the Synthesis of Custom Analog Circuits
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
Michael Krasnicki, Rodney Phelps, James R. Hellums...
DATE
2009
IEEE
149views Hardware» more  DATE 2009»
15 years 11 months ago
An ILP formulation for task mapping and scheduling on multi-core architectures
Multi-core architectures are increasingly being adopted in the design of emerging complex embedded systems. Key issues of designing such systems are on-chip interconnects, memory a...
Ying Yi, Wei Han, Xin Zhao, Ahmet T. Erdogan, Tugh...