1151 search results - page 76 / 231 » Automatic Generation of Complex Properties for Hardware Desi... |
DATE
2007
IEEE
15 years 10 months ago
2007
IEEE
Formal verification is an important issue in circuit and system design. In this context, Bounded Model Checking (BMC) is one of the most successful techniques. But even if all sp...
105
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FPL
2007
Springer
15 years 10 months ago
2007
Springer
In this paper we present an automatic design flow for generating customized embedded FPGA (eFPGA) fabric and a domain specific SOC+eFPGA architecture. This design flow encompas...
153
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VTS
2008
IEEE
15 years 10 months ago
2008
IEEE
Timing-related defects are becoming increasingly important in nanometer technology designs. Small delay variations induced by crosstalk, process variations, powersupply noise, as ...
150
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ICCAD
2003
IEEE
15 years 9 months ago
2003
IEEE
: This paper presents FROSTY, a computer program for automatically extracting the hierarchy of a large-scale digital CMOS circuit from its transistor-level netlist description and ...
192
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DATE
2006
IEEE
15 years 10 months ago
2006
IEEE
same level of system-level CAD support that is now commonplace in the IC industry.Recent advances in microfluidics are expected to lead to sensor systems for high-throughput bioche...