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ITC
1998
IEEE
95views Hardware» more  ITC 1998»
13 years 11 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham
ICCAD
2002
IEEE
176views Hardware» more  ICCAD 2002»
14 years 4 months ago
High capacity and automatic functional extraction tool for industrial VLSI circuit designs
In this paper we present an advanced functional extraction tool for automatic generation of high-level RTL from switch-level circuit netlist representation. The tool is called FEV...
Sasha Novakovsky, Shy Shyman, Ziyad Hanna
VLSID
2003
IEEE
147views VLSI» more  VLSID 2003»
14 years 8 months ago
SoC Synthesis with Automatic Hardware Software Interface Generation
Design of efficient System-on-Chips (SoCs) require thorough application analysis to identify various compute intensive parts. These compute intensive parts can be mapped to hardwa...
Amarjeet Singh 0002, Amit Chhabra, Anup Gangwar, B...
IOLTS
2008
IEEE
117views Hardware» more  IOLTS 2008»
14 years 1 months ago
Verification and Analysis of Self-Checking Properties through ATPG
Present and future semiconductor technologies are characterized by increasing parameters variations as well as an increasing susceptibility to external disturbances. Transient err...
Marc Hunger, Sybille Hellebrand
FDL
2005
IEEE
14 years 1 months ago
Automatic synthesis of the Hardware/Software Interface
Although Moore’s Law enables a huge number of components to be integrated into a single chip, design methods that will allow system architects to put the components together to ...
Francesco Regazzoni, André C. Nácul,...