302 search results - page 11 / 61 » Automatic microarchitectural pipelining |
DAC
2012
ACM
12 years 6 days ago
2012
ACM
In this work we address the problem of managing interconnect timing in high-level synthesis by generating a layoutfriendly microarchitecture. A metric called spreading score is pr...
ICCAD
1994
IEEE
14 years 1 months ago
1994
IEEE
Abstract-- The design of application-specific instruction set processor (ASIP) system includes at least three interdependent tasks: microarchitecture design, instruction set design...
MICRO
2002
IEEE
14 years 2 months ago
2002
IEEE
To find the best designs, architects must rapidly simulate many design alternatives and have confidence in the results. Unfortunately, the most prevalent simulator construction ...
DAC
2010
ACM
13 years 10 months ago
2010
ACM
We present a technique to automatically synthesize a multithreaded in-order pipeline from a high-level unpipelined datapath specification. This work extends the previously propose...
DATE
2010
IEEE
13 years 10 months ago
2010
IEEE
Abstract—We present a transactional datapath specification (Tspec) and the tool (T-piper) to synthesize automatically an inpelined implementation from it. T-spec abstractly views...