Sciweavers

37 search results - page 4 / 8
» BDD-based synthesis of reversible logic for large functions
Sort
View
DAC
2006
ACM
14 years 9 months ago
Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability
- Classical two-variable symmetries play an important role in many EDA applications, ranging from logic synthesis to formal verification. This paper proposes a complete circuit-bas...
Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, ...
DAC
2005
ACM
14 years 9 months ago
A new canonical form for fast boolean matching in logic synthesis and verification
? An efficient and compact canonical form is proposed for the Boolean matching problem under permutation and complementation of variables. In addition an efficient algorithm for co...
Afshin Abdollahi, Massoud Pedram
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 9 months ago
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
ICCAD
2007
IEEE
164views Hardware» more  ICCAD 2007»
14 years 5 months ago
Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates
— Small gates, such as AND2, XOR2 and MUX2, have been mixed with lookup tables (LUTs) inside the programmable logic block (PLB) to reduce area and power and increase performance ...
Yu Hu, Satyaki Das, Steven Trimberger, Lei He
CODES
2005
IEEE
14 years 2 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...