233 search results - page 37 / 47 » Balance Testing of Logic Circuits |
DATE
2003
IEEE
14 years 27 days ago
2003
IEEE
In modern SoCs, embedded memories occupy the largest part of the chip area and include an even larger amount of active devices. As memories are designed very tightly to the limits...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Redundancy-addition-and-removal is a rewiring technique which for a given target wire wt finds a redundant alternative wire wa. Addition of wa makes wt redundant and hence removab...
ISMVL
2007
IEEE
14 years 1 months ago
2007
IEEE
The clock rate of modern chips is still increasing and at the same time the gate size decreases. As a result, already slight variations during the production process may cause a f...
ITC
2003
IEEE
14 years 26 days ago
2003
IEEE
We present an efficient algorithm for identification of two-line bridges in combinational CMOS logic that narrows down the two-line bridge candidates based on tester responses for...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
VLSI timing analysis and power estimation target the same circuit switching activity. Power estimation techniques are categorized as (1) static, (2) statistical, and (3) simulatio...