233 search results - page 40 / 47 » Balance Testing of Logic Circuits |
AHS
2006
IEEE
14 years 2 months ago
2006
IEEE
Domain-specific reconfigurable arrays have shown to provide an efficient trade-off between flexibility of FPGA and performance of ASIC circuit. Nonetheless, the design of these he...
GLVLSI
2007
IEEE
13 years 10 months ago
2007
IEEE
Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders ...
ICCAD
2004
IEEE
14 years 5 months ago
2004
IEEE
— In deep sub-micron technologies, process variations can cause significant path delay and clock skew uncertainties thereby lead to timing failure and yield loss. In this paper,...
ISQED
2006
IEEE
14 years 2 months ago
2006
IEEE
As transistor counts keep increasing and clock frequencies rise, high power consumption is becoming one of the most important obstacles, preventing further scaling and performance...
DAC
2008
ACM
14 years 9 months ago
2008
ACM
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written...