55 search results - page 7 / 11 » Balancing Logic Utilization and Area Efficiency in FPGAs |
FPL
2010
Springer
13 years 5 months ago
2010
Springer
When utilizing reconfigurable hardware there are many applications that will require more memory than is available in a single hardware block. While FPGAs have tools and mechanisms...
ISCAS
2005
IEEE
14 years 1 months ago
2005
IEEE
— Significant headway has been made in logic density and performance of FPGAs in the past decade. Power efficiency of FPGA architectures is arguably the next most important crite...
FCCM
1999
IEEE
13 years 12 months ago
1999
IEEE
The time it takes to reconfigure FPGAs can be a significant overhead for reconfigurable computing. In this paper we develop new compression algorithms for FPGA configurations that...
NOCS
2007
IEEE
14 years 1 months ago
2007
IEEE
We present a novel network-on-chip-based architecture for future programmable chips (FPGAs). A key challenge for FPGA design is supporting numerous highly variable design instance...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
As device size shrinks to the nanometer range, FPGAs are increasingly prone to manufacturing defects. We anticipate that the ability to tolerate multiple defects will be very impo...