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MICRO
2000
IEEE
121views Hardware» more  MICRO 2000»
14 years 1 months ago
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures
Conventional microarchitectures choose a single memory hierarchy design point targeted at the average application. In this paper, we propose a cache and TLB layout and design that...
Rajeev Balasubramonian, David H. Albonesi, Alper B...
SBACPAD
2004
IEEE
105views Hardware» more  SBACPAD 2004»
13 years 11 months ago
Cache Filtering Techniques to Reduce the Negative Impact of Useless Speculative Memory References on Processor Performance
High-performance processors employ aggressive speculation and prefetching techniques to increase performance. Speculative memory references caused by these techniques sometimes br...
Onur Mutlu, Hyesoon Kim, David N. Armstrong, Yale ...
HPCA
2006
IEEE
14 years 10 months ago
Last level cache (LLC) performance of data mining workloads on a CMP - a case study of parallel bioinformatics workloads
With the continuing growth in the amount of genetic data, members of the bioinformatics community are developing a variety of data-mining applications to understand the data and d...
Aamer Jaleel, Matthew Mattina, Bruce L. Jacob
ISLPED
2005
ACM
150views Hardware» more  ISLPED 2005»
14 years 3 months ago
Fast configurable-cache tuning with a unified second-level cache
Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption. Previous tuning methods use a level one configurable cache only, or...
Ann Gordon-Ross, Frank Vahid, Nikil D. Dutt
WAIM
2004
Springer
14 years 3 months ago
Performance Evaluations of Replacement Algorithms in Hierarchical Web Caching
Abstract. Web caching plays an important role in many network services. Utilization of the cache in each level (server, proxy, and client) of network forms a web caching hierarchy....
Haohuan Fu, Pui-on Au, Weijia Jia