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ASPDAC
1999
ACM
151views Hardware» more  ASPDAC 1999»
13 years 11 months ago
Benchmark Circuits Improve the Quality of a Standard Cell Library
-- The experience of designing and employing two benchmark circuits to improve the quality of a standard cell library is reported. It isfound that most of the errors can be uncover...
Rung-Bin Lin, Isaac Shuo-Hsiu Chou, Chi-Ming Tsai
DAC
1997
ACM
13 years 10 months ago
Developing a Concurrent Methodology for Standard-Cell Library Generation
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
Donald G. Baltus, Thomas Varga, Robert C. Armstron...
ISPD
2010
ACM
205views Hardware» more  ISPD 2010»
14 years 1 months ago
Total sensitivity based dfm optimization of standard library cells
Standard cells are fundamental circuit building blocks designed at very early design stages. Nanometer standard cells are prone to lithography proximity and process variations. Ho...
Yongchan Ban, Savithri Sundareswaran, David Z. Pan
ISQED
2006
IEEE
155views Hardware» more  ISQED 2006»
14 years 18 days ago
FASER: Fast Analysis of Soft Error Susceptibility for Cell-Based Designs
This paper is concerned with statically analyzing the susceptibility of arbitrary combinational circuits to single event upsets that are becoming a significant concern for reliabi...
Bin Zhang, Wei-Shen Wang, Michael Orshansky
TCAD
1998
126views more  TCAD 1998»
13 years 6 months ago
Iterative remapping for logic circuits
Abstract—This paper presents an aggressive optimization technique targeting combinational logic circuits. Starting from an initial implementation mapped on a given technology lib...
Luca Benini, Patrick Vuillod, Giovanni De Micheli