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» Benchmark Circuits Improve the Quality of a Standard Cell Li...
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DATE
2008
IEEE
118views Hardware» more  DATE 2008»
13 years 8 months ago
Layout Level Timing Optimization by Leveraging Active Area Dependent Mobility of Strained-Silicon Devices
Advanced MOSFETs such as Strained Silicon (SS) devices have emerged as critical enablers to keep Moore's law on track for sub100nm technologies. Use of Strained Silicon devic...
Ashutosh Chakraborty, Sean X. Shi, David Z. Pan
ISCAS
2006
IEEE
162views Hardware» more  ISCAS 2006»
14 years 22 days ago
Combined image signal processing for CMOS image sensors
This paper presents an efficient image signal processing structure for CMOS image sensors to achieve low area and power consumption. Although CMOS image sensors (CISs) have variou...
Kimo Kim, In-Cheol Park
ICCAD
1998
IEEE
65views Hardware» more  ICCAD 1998»
13 years 11 months ago
Multiway partitioning with pairwise movement
It is known to many researchers in the partitioning community that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway part...
Jason Cong, Sung Kyu Lim
ICCAD
1997
IEEE
69views Hardware» more  ICCAD 1997»
13 years 11 months ago
Speeding up technology-independent timing optimization by network partitioning
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...
Rajat Aggarwal, Rajeev Murgai, Masahiro Fujita
CODES
2005
IEEE
14 years 10 days ago
SOMA: a tool for synthesizing and optimizing memory accesses in ASICs
Arbitrary memory dependencies and variable latency memory systems are major obstacles to the synthesis of large-scale ASIC systems in high-level synthesis. This paper presents SOM...
Girish Venkataramani, Tiberiu Chelcea, Seth Copen ...