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» Bounded-lifetime integrated circuits
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ASPDAC
2010
ACM
135views Hardware» more  ASPDAC 2010»
13 years 4 months ago
Efficient power grid integrity analysis using on-the-fly error check and reduction
In this paper, we present a new voltage IR drop analysis approach for large on-chip power delivery networks. The new approach is based on recently proposed sampling based reductio...
Duo Li, Sheldon X.-D. Tan, Ning Mi, Yici Cai
DAC
2008
ACM
13 years 8 months ago
Technology exploration for graphene nanoribbon FETs
Graphene nanoribbon FETs (GNRFETs) are promising devices for beyond-CMOS nanoelectronics because of their excellent carrier transport properties and potential for large scale proc...
Mihir R. Choudhury, Youngki Yoon, Jing Guo, Kartik...
ISCAS
2002
IEEE
84views Hardware» more  ISCAS 2002»
13 years 11 months ago
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a ...
Jeng-Jie Peng, Ming-Dou Ker, Hsin-Chin Jiang
CDES
2006
100views Hardware» more  CDES 2006»
13 years 8 months ago
Integrity and Integration Issues for Nano-Tube Based Interconnect Systems
: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
Tulin Mangir
ISQED
2002
IEEE
137views Hardware» more  ISQED 2002»
13 years 11 months ago
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits
In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit ar...
Syed M. Alam, Donald E. Troxel, Carl V. Thompson