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MICRO
2009
IEEE
160views Hardware» more  MICRO 2009»
14 years 2 months ago
Variation-tolerant non-uniform 3D cache management in die stacked multicore processor
Process variations in integrated circuits have significant impact on their performance, leakage and stability. This is particularly evident in large, regular and dense structures...
Bo Zhao, Yu Du, Youtao Zhang, Jun Yang 0002
MICRO
2009
IEEE
148views Hardware» more  MICRO 2009»
14 years 2 months ago
Flip-N-Write: a simple deterministic technique to improve PRAM write performance, energy and endurance
The phase-change random access memory (PRAM) technology is fast maturing to production levels. Main advantages of PRAM are non-volatility, byte addressability, in-place programmab...
Sangyeun Cho, Hyunjin Lee
ICCD
2008
IEEE
142views Hardware» more  ICCD 2008»
14 years 1 months ago
Gate planning during placement for gated clock network
Abstract— Clock gating is a popular technique for reducing power dissipation in clock network. Although there have been numerous research efforts on clock gating, the previous ap...
Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu
IEEEPACT
2008
IEEE
14 years 1 months ago
Skewed redundancy
Technology scaling in integrated circuits has consistently provided dramatic performance improvements in modern microprocessors. However, increasing device counts and decreasing o...
Gordon B. Bell, Mikko H. Lipasti
ISCA
2007
IEEE
106views Hardware» more  ISCA 2007»
14 years 1 months ago
Architectural implications of brick and mortar silicon manufacturing
We introduce a novel chip fabrication technique called “brick and mortar”, in which chips are made from small, pre-fabricated ASIC bricks and bonded in a designer-specified a...
Martha Mercaldi Kim, Mojtaba Mehrara, Mark Oskin, ...