69 search results - page 7 / 14 » Buffer insertion for clock delay and skew minimization |
ASPDAC
2004
ACM
14 years 1 months ago
2004
ACM
As gate delays decrease faster than wire delays for each technology generation, buffer insertion becomes a popular method to reduce the interconnect delay. Several modern buffer in...
VLSID
2003
IEEE
14 years 8 months ago
2003
IEEE
We consider the problem of minimizing the delay in transporting a signal across a distance in a VLSI circuit.The problem can be restated as a combined buffer insertion, buffer siz...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
Clock skew minimization is always very important in the clock tree synthesis. Due to clock gating, the clock tree may include different types of logic gates, e.g., AND gates, OR g...
ICCAD
1997
IEEE
14 years 2 days ago
1997
IEEE
† This paper describes a novel methodology to automate the design of the interconnect distribution for multistage clock circuits. We introduce two key ideas. First, a hierarchica...
EURODAC
1995
IEEE
13 years 11 months ago
1995
IEEE
Most existing performance-driven and clock routing algorithms can not guarantee performance after all nets are routed. This paper proposes a new post routing approach which can re...