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FPGA
1998
ACM
153views FPGA» more  FPGA 1998»
14 years 3 months ago
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays
It has become clear that large embedded con gurable memory arrays will be essential in future FPGAs. Embedded arrays provide high-density high-speed implementations of the storage...
Steven J. E. Wilton
IOLTS
2006
IEEE
102views Hardware» more  IOLTS 2006»
14 years 5 months ago
Emulation-based Fault Injection in Circuits with Embedded Memories
FPGA emulation has proven to be a performance effective method to analyse the behaviour of digital circuits in the presence of soft errors due to SEU effects. In particular, the r...
Mario García-Valderas, Marta Portela-Garc&i...
FPL
2005
Springer
96views Hardware» more  FPL 2005»
14 years 4 months ago
FPGA PLB Evaluation using Quantified Boolean Satisfiability
This paper describes a novel Field Programmable Gate Array (FPGA) logic synthesis technique which determines if a logic function can be implemented in a given programmable circuit...
Andrew C. Ling, Deshanand P. Singh, Stephen Dean B...
ISVLSI
2008
IEEE
156views VLSI» more  ISVLSI 2008»
14 years 5 months ago
Characterisation of FPGA Clock Variability
As integrated circuits are scaled down it becomes difficult to maintain uniformity in process parameters across each individual die. The resulting performance variation requires ...
N. Pete Sedcole, Justin S. Wong, Peter Y. K. Cheun...
FPGA
1998
ACM
125views FPGA» more  FPGA 1998»
14 years 3 months ago
Timing Driven Floorplanning on Programmable Hierarchical Targets
The goal of this paper is to perform a timing optimization of a circuit described by a network of cells on a target structure whose connection delays have discrete values following...
S. A. Senouci, A. Amoura, Helena Krupnova, Gabriel...