: As we continue miniaturization of circuits into nano-scale, interconnects have been recognized as the limiting factor for next generation of computing structures. To increase the...
In this paper, a comprehensive and fast method is presented for the timing analysis of process variations on single-walled carbon nanotube (SWCNT) bundles. Unlike previous works t...
—This paper introduces a novel numerical carbon nanotube transistor (CNT) modelling approach which brings in a flexible and efficient cubic spline non-linear approximation of t...
Dafeng Zhou, Tom J. Kazmierski, Bashir M. Al-Hashi...
Recent progress on nanodevices, such as carbon nanotubes and nanowires, points to promising directions for future circuit design. However, nanofabrication techniques are not yet m...
— As silicon CMOS devices are scaled down into the nanoscale regime, new challenges at both the device and system level are arising. While some of these challenges will be overco...