285 search results - page 9 / 57 » Cell architecture for nanoelectronic design |
TVLSI
2010
13 years 2 months ago
2010
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
Abstract - This paper describes the development of a concurrent methodology for standard cell library generation. Use of a novel physical design automation method enables a high de...
ASPDAC
2000
ACM
13 years 12 months ago
2000
ACM
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
DAC
2007
ACM
14 years 8 months ago
2007
ACM
With increasing time-to-market pressure and shortening semiconductor product cycles, more and more chips are being designed with library-based methodologies. In spite of this shif...
DAC
2010
ACM
13 years 11 months ago
2010
ACM
NBTI has been a major aging mechanism for advanced CMOS technology and PBTI is also looming as a big concern. This work first proposes a compact on-chip sensor design that tracks ...