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» Challenges in Physical Chip Design
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MICRO
2008
IEEE
137views Hardware» more  MICRO 2008»
13 years 8 months ago
Verification of chip multiprocessor memory systems using a relaxed scoreboard
Verification of chip multiprocessor memory systems remains challenging. While formal methods have been used to validate protocols, simulation is still the dominant method used to ...
Ofer Shacham, Megan Wachs, Alex Solomatnikov, Amin...
DATE
2005
IEEE
117views Hardware» more  DATE 2005»
14 years 2 months ago
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
As Moore’s Law continues to fuel the ability to build ever increasingly complex system-on-chips (SoCs), achieving performance goals is rising as a critical challenge to completi...
Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew...
ARC
2010
Springer
126views Hardware» more  ARC 2010»
13 years 6 months ago
Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip
The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challe...
Mouna Baklouti, Philippe Marquet, Jean-Luc Dekeyse...
PATMOS
2004
Springer
14 years 2 months ago
A Dual Low Power and Crosstalk Immune Encoding Scheme for System-on-Chip Buses
Abstract. Crosstalk causes logical errors due to data dependent delay degradation as well as energy consumption and is considered the biggest signal integrity challenge for long on...
Zahid Khan, Tughrul Arslan, Ahmet T. Erdogan
CSB
2003
IEEE
14 years 2 months ago
Fast and Sensitive Probe Selection for DNA Chips Using Jumps in Matching Statistics
The design of large scale DNA microarrays is a challenging problem. So far, probe selection algorithms must trade the ability to cope with large scale problems for a loss of accur...
Sven Rahmann