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MEMOCODE
2003
IEEE
14 years 29 days ago
MoDe: A Method for System-Level Architecture Evaluation
System-level design methodologies for embedded HW/SW systems face several challenges: In order to be susceptible to systematic formal analysis based on state-space exploration, a ...
Jan Romberg, Oscar Slotosch, Gabor Hahn
FLAIRS
2007
13 years 10 months ago
Memory-Prediction Framework for Pattern Recognition: Performance and Suitability of the Bayesian Model of Visual Cortex
This paper explores an inferential system for recognizing visual patterns. The system is inspired by a recent memoryprediction theory and models the high-level architecture of the...
Saulius Juozas Garalevicius
CODES
2005
IEEE
14 years 1 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
CF
2004
ACM
14 years 1 months ago
Fault tolerant clockless wave pipeline design
This paper presents a fault tolerant design technique for the clockless wave pipeline. The specific architectural model investigated in this paper is the two-phase clockless asyn...
T. Feng, Byoungjae Jin, J. Wang, Nohpill Park, Yon...
ISLPED
2003
ACM
83views Hardware» more  ISLPED 2003»
14 years 28 days ago
Leakage power modeling and optimization in interconnection networks
Power will be the key limiter to system scalability as interconnection networks take up an increasingly significant portion of system power. In this paper, we propose an architec...
Xuning Chen, Li-Shiuan Peh