253 search results - page 17 / 51 » Circuit partitions and |
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Methods based on Boolean satisfiability (SAT) typically use a Conjunctive Normal Form (CNF) representation of the Boolean formula, and exploit the structure of the given problem ...
DAC
1994
ACM
13 years 12 months ago
1994
ACM
A low overhead DFT technique, called clock-grouping, for delay testing of sequential synchronous circuits is presented. The proposed technique increases robust path delay fault co...
DAC
1997
ACM
13 years 12 months ago
1997
ACM
In this paper, we present a new hypergraph partitioning algorithm that is based on the multilevel paradigm. In the multilevel paradigm, a sequence of successively coarser hypergra...
ICCAD
1998
IEEE
14 years 1 days ago
1998
IEEE
It is known to many researchers in the partitioning community that the recursive bipartitioning approach outperforms the direct non-recursive approach in solving the multiway part...
ICCAD
1997
IEEE
14 years 11 hour ago
1997
IEEE
Technology-independenttimingoptimizationis animportantproblem in logic synthesis. Although many promising techniques have been proposed in the past, unfortunately they are quite s...