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DAC
1996
ACM
13 years 12 months ago
A Probability-Based Approach to VLSI Circuit Partitioning
Iterative-improvement 2-way min-cut partitioning is an important phase in most circuit partitioning tools. Most iterative improvement techniques for circuit netlists like the Fidd...
Shantanu Dutt, Wenyong Deng
ASPDAC
1999
ACM
132views Hardware» more  ASPDAC 1999»
14 years 2 days ago
Faster and Better Spectral Algorithms for Multi-Way Partitioning
In this paper, two faster and better spectral algorithms are presented for the multi-way circuit partitioning problem with the objective of minimizing the Scaled Cost. As pointed ...
Jan-Yang Chang, Yu-Chen Liu, Ting-Chi Wang
ICCAD
2002
IEEE
100views Hardware» more  ICCAD 2002»
14 years 4 months ago
Multi-objective circuit partitioning for cutsize and path-based delay minimization
– In this paper we present multi-objective hMetis partitioning for simultaneous cutsize and circuit delay minimization. We change the partitioning process itself by introducing a...
Cristinel Ababei, Navaratnasothie Selvakkumaran, K...
FPGA
1995
ACM
116views FPGA» more  FPGA 1995»
13 years 11 months ago
Logic Partition Orderings for Multi-FPGA Systems
One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning...
Scott Hauck, Gaetano Borriello
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 8 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy