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» Clock gating architectures for FPGA power reduction
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DAC
2007
ACM
14 years 11 months ago
Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip
Due to high levels of integration and complexity, the design of multi-core SoCs has become increasingly challenging. In particular, energy consumption and distributing a single gl...
Ümit Y. Ogras, Diana Marculescu, Puru Choudha...
ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 7 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
DATE
2006
IEEE
120views Hardware» more  DATE 2006»
14 years 4 months ago
Design and test of fixed-point multimedia co-processor for mobile applications
: In this research, a fixed-point multimedia co-processor is designed and tested into an ARM-10 based mobile graphics processor for portable 2-D and 3-D multimedia applications. Th...
Ju-Ho Sohn, Jeong-Ho Woo, Jerald Yoo, Hoi-Jun Yoo
ISCAS
2006
IEEE
108views Hardware» more  ISCAS 2006»
14 years 4 months ago
DSP engine design for LINC wireless transmitter systems
—Linear amplification with nonlinear components (LINC) technique is a linearization technique for power amplifier designs. By using LINC, the nonlinear power amplifier with high ...
Kai-Yuan Jheng, Yi-Chiuan Wang, An-Yeu Wu, Hen-Wai...
IPPS
2006
IEEE
14 years 4 months ago
Multi-clock pipelined design of an IEEE 802.11a physical layer transmitter
Among different wireless LAN technologies 802.11a has recently become popular due to its high throughput, large system capacity, and relatively long range. In this paper, we prop...
Maryam Mizani, Daler N. Rakhmatov