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ASAP
2005
IEEE
87views Hardware» more  ASAP 2005»
14 years 2 months ago
Expression Synthesis in Process Networks generated by LAURA
The COMPAAN/LAURA [18] tool chain maps nested loop applications written in Matlab onto reconfigurable platforms, such as FPGAs. COMPAAN rewrites the original Matlab application a...
Claudiu Zissulescu, Bart Kienhuis, Ed F. Depretter...
ICCAD
2006
IEEE
177views Hardware» more  ICCAD 2006»
14 years 5 months ago
Application-specific customization of parameterized FPGA soft-core processors
Soft-core microprocessors mapped onto field-programmable gate arrays (FPGAs) represent an increasingly common embedded software implementation option. Modern FPGA soft-cores are p...
David Sheldon, Rakesh Kumar, Roman L. Lysecky, Fra...
CASES
2007
ACM
14 years 27 days ago
Performance optimal processor throttling under thermal constraints
We derive analytically, the performance optimal throttling curve for a processor under thermal constraints for a given task sequence. We found that keeping the chip temperature co...
Ravishankar Rao, Sarma B. K. Vrudhula
CODES
2001
IEEE
14 years 17 days ago
Evaluating register file size in ASIP design
Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A ke...
Manoj Kumar Jain, Lars Wehmeyer, Stefan Steinke, P...
CF
2010
ACM
14 years 2 months ago
Proposition for a sequential accelerator in future general-purpose manycore processors and the problem of migration-induced cach
As the number of transistors on a chip doubles with every technology generation, the number of on-chip cores also increases rapidly, making possible in a foreseeable future to des...
Pierre Michaud, Yiannakis Sazeides, André S...