559 search results - page 20 / 112 » Compiling Image Processing Applications to Reconfigurable Ha... |
DAC
2003
ACM
14 years 8 months ago
2003
ACM
In this paper, we describe a set of compiler analyses and an implementation that automatically map a sequential and un-annotated C program into a pipelined implementation, targete...
ASAP
2006
IEEE
14 years 1 months ago
2006
IEEE
Massively parallel processor array architectures can be used as hardware accelerators for a plenty of dataflow dominant applications. Bilateral filtering is an example of a stat...
ICCAD
2001
IEEE
14 years 4 months ago
2001
IEEE
Efficient high level design tools that can map behavioral descriptions to FPGA architectures are one of the key requirements to fully leverage FPGA for high throughput computatio...
ERSA
2009
13 years 5 months ago
2009
We present the architecture and programming model for MORA, a coarse-grained reconfigurable processor aimed at multimedia applications. The MORA architecure is a MIMD machine consi...
CHES
2003
Springer
13 years 11 months ago
2003
Springer
Abstract. Performance evaluation of the Advanced Encryption Standard candidates has led to intensive study of both hardware and software implementations. However, although plentifu...