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» Complementarity of Error Detection Techniques
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MICRO
2007
IEEE
188views Hardware» more  MICRO 2007»
14 years 1 months ago
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding
In deep sub-micron ICs, growing amounts of ondie memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses...
Jangwoo Kim, Nikos Hardavellas, Ken Mai, Babak Fal...
VTS
1999
IEEE
125views Hardware» more  VTS 1999»
13 years 12 months ago
Error Detecting Refreshment for Embedded DRAMs
This paper presents a new technique for on-line consistency checking of embedded DRAMs. The basic idea is to use the periodic refresh operation for concurrently computing a test c...
Sybille Hellebrand, Hans-Joachim Wunderlich, Alexa...
DATE
2003
IEEE
105views Hardware» more  DATE 2003»
14 years 27 days ago
Detecting Soft Errors by a Purely Software Approach: Method, Tools and Experimental Results
In this paper is described a software technique allowing to detect soft errors occurring in processor-based digital architectures. The detection mechanism is based on a set of rul...
B. Nicolescu, Raoul Velazco
DATE
2000
IEEE
90views Hardware» more  DATE 2000»
14 years 11 hour ago
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique
: IC technologies are approaching the ultimate limits of silicon in terms of channel width, power supply and speed. By approaching these limits, circuits are becoming increasingly ...
Lorena Anghel, Michael Nicolaidis
DSD
2006
IEEE
113views Hardware» more  DSD 2006»
13 years 9 months ago
Cascade Scheme for Concurrent Errors Detection
The paper deals with synthesis technique for designing circuits with cascade errors detection. The proposed technique is based on partitioning a scheme into a number of cascades f...
Ilya Levin, Vladimir Ostrovsky, Osnat Keren, Vladi...