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DAC
2008
ACM
14 years 10 months ago
Transistor level gate modeling for accurate and fast timing, noise, and power analysis
Current source based cell models are becoming a necessity for accurate timing and noise analysis at 65nm and below. Voltage waveform shapes are increasingly more difficult to repr...
S. Raja, F. Varadi, Murat R. Becer, Joao Geada
VLSID
2002
IEEE
129views VLSI» more  VLSID 2002»
14 years 10 months ago
Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis
In this paper, we explore the concept of using analytical models to efficiently generate delay change curves (DCCs) that can then be used to characterize the impact of noise on an...
Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylves...
ICCD
2008
IEEE
150views Hardware» more  ICCD 2008»
14 years 6 months ago
Timing analysis considering IR drop waveforms in power gating designs
—IR drop noise has become a critical issue in advanced process technologies. Traditionally, timing analysis in which the IR drop noise is considered assumes a worst-case IR drop ...
Shih-Hung Weng, Yu-Min Kuo, Shih-Chieh Chang, Malg...
ICCAD
2005
IEEE
133views Hardware» more  ICCAD 2005»
14 years 6 months ago
Gate sizing using incremental parameterized statistical timing analysis
— As technology scales into the sub-90nm domain, manufacturing variations become an increasingly significant portion of circuit delay. As a result, delays must be modeled as sta...
Matthew R. Guthaus, Natesan Venkateswaran, Chandu ...
IESS
2007
Springer
110views Hardware» more  IESS 2007»
14 years 3 months ago
Run-Time efficient Feasibility Analysis of Uni-Processor Systems with Static Priorities
: The performance of feasibility tests is crucial in many applications. When using feasibility tests online only a limited amount of analysis time is available. Run-time efficiency...
Karsten Albers, Frank Bodmann, Frank Slomka