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DAC
1998
ACM
14 years 10 months ago
Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs
The logic blocks CLBs of a lookup table LUT based FPGA consist of one or more LUTs, possibly of di erent sizes. In this paper, we focus on technology mapping for CLBs with several...
Madhukar R. Korupolu, K. K. Lee, D. F. Wong
DAC
1999
ACM
14 years 10 months ago
A Multiscale Method for Fast Capacitance Extraction
The many levels of metal used in aggressive deep submicron process technologies has made fast and accurate capacitance extraction of complicated 3-D geometries of conductors essen...
Johannes Tausch, Jacob K. White
DAC
2000
ACM
14 years 10 months ago
On switch factor based analysis of coupled RC interconnects
We revisit a basic element of modern signal integrity analysis, the modeling of worst-case coupling capacitance effects within a switch factor (SF) based methodology. We show that...
Andrew B. Kahng, Sudhakar Muddu, Egino Sarto
DAC
2001
ACM
14 years 10 months ago
Clustered VLIW Architectures with Predicated Switching
In order to meet the high throughput requirements of applications exhibiting high ILP, VLIW ASIPs may increasingly include large numbers of functional unitsFUs. Unfortunately, `sw...
Margarida F. Jacome, Gustavo de Veciana, Satish Pi...
DAC
2003
ACM
14 years 10 months ago
Performance-impact limited area fill synthesis
Chemical-mechanical planarization (CMP) and other manufacturing steps in very deep-submicron VLSI have varying effects on device and interconnect features, depending on the local ...
Yu Chen, Puneet Gupta, Andrew B. Kahng
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