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GLVLSI
2009
IEEE
150views VLSI» more  GLVLSI 2009»
14 years 2 months ago
Contradictory antecedent debugging in bounded model checking
In the context of formal verification Bounded Model Checking (BMC) has shown to be very powerful for large industrial designs. BMC is used to check whether a circuit satisfies a...
Daniel Große, Robert Wille, Ulrich Kühn...
GECCO
2007
Springer
186views Optimization» more  GECCO 2007»
14 years 1 months ago
ICSPEA: evolutionary five-axis milling path optimisation
ICSPEA is a novel multi-objective evolutionary algorithm which integrates aspects from the powerful variation operators of the Covariance Matrix Adaptation Evolution Strategy (CMA...
Jörn Mehnen, Rajkumar Roy, Petra Kersting, To...
GLVLSI
2002
IEEE
109views VLSI» more  GLVLSI 2002»
14 years 15 days ago
Minimizing resources in a repeating schedule for a split-node data-flow graph
Many computation-intensive or recursive applications commonly found in digital signal processing and image processing applications can be represented by data-flow graphs (DFGs). ...
Timothy W. O'Neil, Edwin Hsing-Mean Sha
ISSS
2002
IEEE
127views Hardware» more  ISSS 2002»
14 years 14 days ago
Validation in a Component-Based Design Flow for Multicore SoCs
Currently, since many SoCs include heterogeneous components such as CPUs, DSPs, ASICs, memories, buses, etc., system integration becomes a major step in the design flow. To enable...
Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima,...
SMA
2008
ACM
192views Solid Modeling» more  SMA 2008»
13 years 6 months ago
Identification of sections from engineering drawings based on evidence theory
View identification is the basal process for solid reconstruction from engineering drawings. A new method is presented to label various views from a section-involved drawing and i...
Jie-Hui Gong, Hui Zhang, Bin Jiang, Jia-Guang Sun