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DATE
2010
IEEE
157views Hardware» more  DATE 2010»
14 years 23 days ago
RMOT: Recursion in model order for task execution time estimation in a software pipeline
Abstract—This paper addresses the problem of execution time estimation for tasks in a software pipeline independent of the application structure or the underlying architecture. A...
Nabeel Iqbal, M. A. Siddique, Jörg Henkel
DATE
2010
IEEE
154views Hardware» more  DATE 2010»
14 years 23 days ago
ERSA: Error Resilient System Architecture for probabilistic applications
There is a growing concern about the increasing vulnerability of future computing systems to errors in the underlying hardware. Traditional redundancy techniques are expensive for...
Larkhoon Leem, Hyungmin Cho, Jason Bau, Quinn A. J...
GLVLSI
2010
IEEE
164views VLSI» more  GLVLSI 2010»
14 years 23 days ago
Performance and energy trade-offs analysis of L2 on-chip cache architectures for embedded MPSoCs
On-chip memory organization is one of the most important aspects that can influence the overall system behavior in multiprocessor systems. Following the trend set by high-perform...
Mohamed M. Sabry, Martino Ruggiero, Pablo Garcia D...
ISCA
2010
IEEE
205views Hardware» more  ISCA 2010»
14 years 23 days ago
The virtual write queue: coordinating DRAM and last-level cache policies
In computer architecture, caches have primarily been viewed as a means to hide memory latency from the CPU. Cache policies have focused on anticipating the CPU’s data needs, and...
Jeffrey Stuecheli, Dimitris Kaseridis, David Daly,...
ISCA
2010
IEEE
210views Hardware» more  ISCA 2010»
14 years 23 days ago
An intra-chip free-space optical interconnect
Continued device scaling enables microprocessors and other systems-on-chip (SoCs) to increase their performance, functionality, and hence, complexity. Simultaneously, relentless s...
Jing Xue, Alok Garg, Berkehan Ciftcioglu, Jianyun ...
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