62 search results - page 10 / 13 » Concurrent Fault Detection in Random Combinational Logic |
DAC
2008
ACM
14 years 7 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...
ITC
1998
IEEE
13 years 11 months ago
1998
IEEE
This paper presents a logic synthesis tool called BETSY (BIST Environment Testable Synthesis) for synthesizing circuits that achieve complete (100%)fault coverage in a user specif...
DATE
2007
IEEE
14 years 1 months ago
2007
IEEE
This paper proposes an efficient test methodology to test switches in a Network-on-Chip (NoC) architecture. A switch in an NoC consists of a number of ports and a router. Using th...
MICRO
2006
IEEE
14 years 21 days ago
2006
IEEE
Although processor design verification consumes ever-increasing resources, many design defects still slip into production silicon. In a few cases, such bugs have caused expensive...
ICST
2008
IEEE
14 years 1 months ago
2008
IEEE
Web applications have rapidly become a critical part of business for many organizations. However, increased usage of web applications has not been reciprocated with corresponding ...