53 search results - page 4 / 11 » Data Speculation Support for a Chip Multiprocessor |
ISCA
2006
IEEE
14 years 1 months ago
2006
IEEE
Transactional Memory (TM), Thread-Level Speculation (TLS), and Checkpointed multiprocessors are three popular architectural techniques based on the execution of multiple, cooperat...
HPCA
1998
IEEE
13 years 11 months ago
1998
IEEE
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...
ISCA
2000
IEEE
13 years 12 months ago
2000
IEEE
While architects understandhow to build cost-effective parallel machines across a wide spectrum of machine sizes (ranging from within a single chip to large-scale servers), the re...
EMSOFT
2005
Springer
14 years 1 months ago
2005
Springer
Recent research in embedded computing indicates that packing multiple processor cores on the same die is an effective way of utilizing the ever-increasing number of transistors. T...
MICRO
2010
IEEE
13 years 5 months ago
2010
IEEE
To extend the exponential performance scaling of future chip multiprocessors, improving energy efficiency has become a first-class priority. Single-chip heterogeneous computing ha...