This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
A new low-power design technique, multirate, has been used along with other methods such as look-ahead, pipelining in designing the cost-effective low-power architectures of video...
This paper presents a new multiprocessor architecture for the parallel execution of logic programs, developed as part of the Aquarius Project. This architecture is designed to sup...
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...