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DATE
2000
IEEE
139views Hardware» more  DATE 2000»
14 years 1 days ago
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation
This paper presents a new approach on combined highlevel synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal...
Oliver Bringmann, Wolfgang Rosenstiel, Carsten Men...
ETS
2006
IEEE
89views Hardware» more  ETS 2006»
13 years 11 months ago
On-Chip Time Measurement Architecture with Femtosecond Timing Resolution
This paper presents a new on-chip time measurement architecture which is based on the Timeto-Digital Conversion (TDC) method that is capable of achieving a timing resolution of te...
Matthew Collins, Bashir M. Al-Hashimi
ISCAS
1999
IEEE
78views Hardware» more  ISCAS 1999»
13 years 12 months ago
Cost-effective low-power architectures of video coding systems
A new low-power design technique, multirate, has been used along with other methods such as look-ahead, pipelining in designing the cost-effective low-power architectures of video...
Jie Chen, K. J. Ray Liu
ISCA
1987
IEEE
65views Hardware» more  ISCA 1987»
13 years 11 months ago
Performance Studies of a Parallel Prolog Architecture
This paper presents a new multiprocessor architecture for the parallel execution of logic programs, developed as part of the Aquarius Project. This architecture is designed to sup...
Barry S. Fagin, Alvin M. Despain
ISSS
2002
IEEE
106views Hardware» more  ISSS 2002»
14 years 17 days ago
Modeling Assembly Instruction Timing in Superscalar Architectures
This paper proposes an original model of the execution time of assembly instructions in superscalar architectures. The approach is based on a rigorous mathematical model and provi...
William Fornaciari, Vito Trianni, Carlo Brandolese...