69 search results - page 7 / 14 » Datapath Synthesis for Standard-Cell Design |
ICCAD
2005
IEEE
14 years 5 months ago
2005
IEEE
We discuss a new synthesis flow, which offers the ability to do easy delay testing almost free in terms of its impact on speed and area as compared to corresponding implementation...
DAC
2000
ACM
14 years 9 months ago
2000
ACM
In this paper we describe an area efficient power minimization scheme "Control Generated ClockingI` that saves significant amounts of power in datapath registers and clock dr...
ISSS
1999
IEEE
14 years 26 days ago
1999
IEEE
This paper describes a mechanism for automatic design and synthesis of very long instruction word (VLIW), and its generalization, explicitly parallel instruction computing rocesso...
DAC
2006
ACM
14 years 9 months ago
2006
ACM
We address the problem of estimating controller delay from high-level specifications during behavioral synthesis. Typically, the critical path of a synthesised behavioral design g...
DATE
2009
IEEE
14 years 3 months ago
2009
IEEE
Abstract—This paper presents a technique to perform arbitrary fixed permutations on streaming data. We describe a parameterized architecture that takes as input n data points st...