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DATE
2003
IEEE
84views Hardware» more  DATE 2003»
14 years 2 months ago
SoC Design and Test Considerations
: Modern SoC Design for high-volume products requires a strong focus on Design-for-Test and Designfor-Manufacturability. We present a case study of an SoC test concept, including a...
Martin Schrader, Roderick McConnell
DATE
2002
IEEE
80views Hardware» more  DATE 2002»
14 years 1 months ago
Test Planning and Design Space Exploration in a Core-Based Environment
This paper proposes a comprehensive model for test planning in a core-based environment. The main contribution of this work is the use of several types of TAMs and the considerati...
Érika F. Cota, Luigi Carro, Marcelo Lubasze...
DATE
1999
IEEE
89views Hardware» more  DATE 1999»
14 years 1 months ago
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement
Complex signal processing algorithms are specified in floating point precision. When their hardware implementation requires fixed point precision, type refinement is needed. The p...
Radim Cmar, Luc Rijnders, Patrick Schaumont, Serge...
DATE
2004
IEEE
135views Hardware» more  DATE 2004»
14 years 15 days ago
A Simulation-Based Power-Aware Architecture Exploration of a Multiprocessor System-on-Chip Design
We present the design exploration of a System-on-Chip architecture dedicated to the implementation of the HIPERLAN/2 communication protocol. The task was accomplished by means of ...
Francesco Menichelli, Mauro Olivieri, Luca Benini,...
DATE
2004
IEEE
149views Hardware» more  DATE 2004»
14 years 15 days ago
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
This paper describes a novel design methodology to implement a secure DPA resistant crypto processor. The methodology is suitable for integration in a common automated standard ce...
Kris Tiri, Ingrid Verbauwhede