11 search results - page 2 / 3 » Defect tolerant probabilistic design paradigm for nanotechno... |
ICCAD
2003
IEEE
14 years 4 months ago
2003
IEEE
As current silicon-based techniques fast approach their practical limits, the investigation of nanoscale electronics, devices and system architectures becomes a central research p...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than ...
MICRO
2006
IEEE
13 years 7 months ago
2006
IEEE
Shrinking devices to the nanoscale, increasing integration densities, and reducing of voltage levels down to the thermal limit, all conspire to produce faulty systems. Frequent oc...
GLVLSI
2009
IEEE
13 years 11 months ago
2009
IEEE
Mounting concerns over variability, defects and noise motivate a new approach for integrated circuits: the design of stochastic logic, that is to say, digital circuitry that opera...
DAC
2008
ACM
14 years 8 months ago
2008
ACM
As integrated circuit technology plumbs ever greater depths in the scaling of feature sizes, maintaining the paradigm of deterministic Boolean computation is increasingly challeng...