424 search results - page 13 / 85 » Delay modelling improvement for low voltage applications |
VLSID
2004
IEEE
14 years 8 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
VLSID
1993
IEEE
13 years 12 months ago
1993
IEEE
High throughput and low latency designs are required in modern high performance systems, especially for signal processing applications. Existing logic families cannot provide both...
DAC
2004
ACM
14 years 8 months ago
2004
ACM
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
WORDS
2003
IEEE
14 years 1 months ago
2003
IEEE
Due to the lack of QoS support, ensuring an acceptable application level QoS for the real-time delivery of multiobject multimedia presentations on the current Internet is very cha...
VLSID
2010
IEEE
13 years 11 months ago
2010
IEEE
In this paper, we propose a new hetero-material stepped gate (HSG) SOI LDMOS in which the gate is divided into three sections - an n+ gate sandwiched between two p+ gates and the ...