4 search results - page 1 / 1 » Delay testing of SOI circuits: Challenges with the history e... |
ITC
1999
IEEE
13 years 11 months ago
1999
IEEE
VTS
2002
IEEE
14 years 19 hour ago
2002
IEEE
Very Low Voltage (VLV) testing has been proposed to increase flaw detection in bulk silicon CMOS integrated circuits and this paper explores these and additional advantages in the...
DAC
2011
ACM
12 years 7 months ago
2011
ACM
Variations in delay caused by within-die and die-to-die process variations and SOI history effect increase timing margins and reduce performance. In order to develop mitigation te...
DAC
2002
ACM
14 years 8 months ago
2002
ACM
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...