50 search results - page 6 / 10 » Design Rewiring Using ATPG |
ITC
1992
IEEE
13 years 11 months ago
1992
IEEE
This paper presents a BIST technique that allows the synchronization of multiple scan chains clocked at different frequencies. The technique is used to improve performance testing...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
The delay fault test pattern set generated by timing unaware commercial ATPG tools mostly affects very short paths, thereby increasing the escape chance of smaller delay defects. ...
IOLTS
2008
IEEE
14 years 1 months ago
2008
IEEE
Sets of Pairs of Functions to be Distinguished (SPFD) is a functional flexibility representation method that was recently introduced in the logic synthesis domain, and promises s...
DAC
2003
ACM
14 years 9 days ago
2003
ACM
To improve the system performance, designs with multiple clocks have become more and more popular. In this paper, several novel test generation procedures are proposed to utilize ...
IOLTS
2009
IEEE
14 years 1 months ago
2009
IEEE
—Robust circuit design has become a major concern for nanoscale technologies. As a consequence, for design validation, not only the functionality of a circuit has to be considere...