50 search results - page 8 / 10 » Design Rewiring Using ATPG |
DAC
2001
ACM
14 years 8 months ago
2001
ACM
roperty Verification by Abstraction Refinement with Formal, Simulation and Hybrid Engines Dong Wang , Pei-Hsin Ho , Jiang Long , James Kukula Yunshan Zhu , Tony Ma , Robert D...
EURODAC
1994
IEEE
14 years 17 hour ago
1994
IEEE
This paper presents a testability improvement method for digital systems described in VHDL behavioral specification. The method is based on testability analysis at registertransfe...
DATE
2009
IEEE
14 years 2 months ago
2009
IEEE
This paper presents a scalable method to generate close to minimal size test pattern sets for stuck-at faults in scan based circuits. The method creates sets of potentially compat...
DATE
2008
IEEE
14 years 2 months ago
2008
IEEE
We present Low Power Illinois scan architecture (LPILS) to achieve power dissipation and test data volume reduction, simultaneously. By using the proposed scan architecture, dynam...
ITC
2000
IEEE
14 years 8 days ago
2000
IEEE
A common approachfor large industrial designs is to use logic built-in self-test (LBIST)followed by test data from an external tester. Because the fault coverage with LBIST alone ...