17 search results - page 3 / 4 » Design and CAD challenges in 45nm CMOS and beyond |
VLSID
2009
IEEE
14 years 8 months ago
2009
IEEE
: The challenges in nano-CMOS circuit design include the following: variability, leakage, power, thermals, reliability, and yield. This talk will focus on interdependent considerat...
DATE
2003
IEEE
14 years 18 days ago
2003
IEEE
An overview of microsystems technology is presented along with a discussion of the recent trends and challenges associated with its development. A typical bottom-up design methodo...
GLVLSI
2010
IEEE
14 years 2 days ago
2010
IEEE
Graphene nanoribbon tunneling FETs (GNR TFETs) are promising devices for post-CMOS low-power applications because of the low subthreshold swing, high Ion/Ioff, and potential for l...
CAD
2002
Springer
13 years 7 months ago
2002
Springer
This paper discusses product variety design under optimization viewpoint. Product variety design means the challenge to simultaneously design multiple products toward higher optim...
TVLSI
2002
13 years 7 months ago
2002
Abstract--This paper provides a high level survey of the increasing effects of on-chip inductance. These effects are classified into desirable and nondesirable effects. Among the u...