— We present a design technique for implementing asynchronous ALUs with CMOS domino logic and delay insensitive dual rail four-phase logic. It ensures economy in silicon area and...
P. Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, ...
This paper describes the design and implementation of the NUMAchine multiprocessor. As the market for CC-NUMA multiprocessors expands, this research project provides a timely arch...
A. Grbic, Stephen Dean Brown, S. Caranci, R. Grind...
Multimedia and communication algorithms from embedded system domain often make extensive use of floating-point arithmetic. Due to the complexity and expense of the floating-poin...
Abstract— In this paper, we describe the design and implementation of the primary memory system of the TRIPS processor. To match the aggressive execution bandwidth and support hi...
Simha Sethumadhavan, Robert G. McDonald, Rajagopal...
—We present a design and implementation of a radix-4 complex division unit with prescaling of the operands. Specifically, we extend the treatment of the residual bound and error...
Pouya Dormiani, Milos D. Ercegovac, Jean-Michel Mu...