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ICCD
2007
IEEE
205views Hardware» more  ICCD 2007»
14 years 3 months ago
Hardware libraries: An architecture for economic acceleration in soft multi-core environments
In single processor architectures, computationallyintensive functions are typically accelerated using hardware accelerators, which exploit the concurrency in the function code to ...
David Meisner, Sherief Reda
MICRO
2008
IEEE
92views Hardware» more  MICRO 2008»
14 years 1 months ago
Online design bug detection: RTL analysis, flexible mechanisms, and evaluation
Higher level of resource integration and the addition of new features in modern multi-processors put a significant pressure on their verification. Although a large amount of res...
Kypros Constantinides, Onur Mutlu, Todd M. Austin
MICRO
2006
IEEE
105views Hardware» more  MICRO 2006»
14 years 23 days ago
Distributed Microarchitectural Protocols in the TRIPS Prototype Processor
Growing on-chip wire delays will cause many future microarchitectures to be distributed, in which hardware resources within a single processor become nodes on one or more switched...
Karthikeyan Sankaralingam, Ramadass Nagarajan, Rob...
CASES
2006
ACM
14 years 22 days ago
High-level power analysis for multi-core chips
Technology trends have led to the advent of multi-core chips in the form of both general-purpose chip multiprocessors (CMPs) and embedded multi-processor systems-on-a-chip (MPSoCs...
Noel Eisley, Vassos Soteriou, Li-Shiuan Peh
MICRO
2008
IEEE
106views Hardware» more  MICRO 2008»
14 years 1 months ago
EVAL: Utilizing processors with variation-induced timing errors
Parameter variation in integrated circuits causes sections of a chip to be slower than others. If, to prevent any resulting timing errors, we design processors for worst-case para...
Smruti R. Sarangi, Brian Greskamp, Abhishek Tiwari...