59 search results - page 6 / 12 » Design for Verification in System-level Models and RTL |
CODES
2007
IEEE
14 years 1 months ago
2007
IEEE
Multiple wireless technologies are converging to run on personal handhelds. The plethora of communication standards next to the cost issues of deeper submicron processing require ...
DAC
2006
ACM
14 years 8 months ago
2006
ACM
or Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdu...
VLSID
2008
IEEE
14 years 8 months ago
2008
IEEE
With increasing adoption of Electronic System Level (ESL) tools, effective design and validation time has reduced to a considerable extent. Cosimulation is found to be a principal...
TCAD
2008
13 years 7 months ago
2008
el Predicate Abstraction and Refinement Techniques for Verifying RTL Verilog Himanshu Jain, Daniel Kroening, Natasha Sharygina, and Edmund M. Clarke, Fellow, IEEE As a first step, ...
DATE
2004
IEEE
13 years 11 months ago
2004
IEEE
In this paper, we present a technique to design and verify the Look-Aside (LA-1) Interface standard used in network processors. Our design flow includes several refinements starti...