59 search results - page 8 / 12 » Design for Verification in System-level Models and RTL |
CODES
2005
IEEE
14 years 1 months ago
2005
IEEE
This paper describes the design of a low-cost, low-power smart imaging core that can be embedded in cameras. The core integrates an ARM 9 processor, a camera interface and two spe...
VLSID
2006
IEEE
14 years 1 months ago
2006
IEEE
This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design c...
ITC
2003
IEEE
14 years 24 days ago
2003
IEEE
Functional verification of complex designs largely relies on the use of simulation in conjunction high-level verification languages (HVL) and test-bench automation (TBA) tools. In...
DATE
2006
IEEE
14 years 1 months ago
2006
IEEE
Most hardware description languages do not enforce determinacy, meaning that they may yield races. Race conditions pose a problem for the implementation, verification, and validat...
DAC
1997
ACM
13 years 11 months ago
1997
ACM
A methodology for architecture exploration of look-up table based decoders is presented. For the degree of parallel processing a trade-off can be made by exploring system level an...