195 search results - page 9 / 39 » Design of clocked circuits using UML |
ISCAS
2006
IEEE
14 years 1 months ago
2006
IEEE
— This paper presents a novel Ternary More, Less and Equality (MLE) Circuit implemented with Recharged SemiFloating Gate Transistors. The circuit is a ternary application, and te...
ISPD
2004
ACM
14 years 1 months ago
2004
ACM
Modern processors and SoCs require the adoption of poweroriented design styles, due to the implications that power consumption may have on reliability, cost and manufacturability ...
ARVLSI
1999
IEEE
14 years 4 days ago
1999
IEEE
We describe a method to clock the domino pipeline at the maximum rate by using soft synchronizers between pipeline stages and thus allowing "time borrowing," i.e., allow...
DAC
2005
ACM
13 years 9 months ago
2005
ACM
This paper presents a new method for designing test wrappers for embedded cores with multiple clock domains. By exploiting the use of multiple shift frequencies, the proposed meth...
ISCAS
2002
IEEE
14 years 22 days ago
2002
IEEE
A novel connection between digit-serialcomputationand skew-tolerant domino circuit design is exploited to create very efficient implementations of FIR digital filters. In our ap...