55 search results - page 10 / 11 » Design of mixed gates for leakage reduction |
DAC
2005
ACM
13 years 10 months ago
2005
ACM
With 90nm CMOS in production and 65nm testing in progress, power has been pushed to the forefront of design metrics. This paper will outline practical techniques that are used to ...
ICCAD
2009
IEEE
13 years 6 months ago
2009
IEEE
As VLSI technology reaches 45nm technology node, leakage power optimization has become a major design challenge. Threshold voltage (vt) assignment has been extensively studied, du...
TVLSI
2010
13 years 3 months ago
2010
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
ISQED
2009
IEEE
14 years 3 months ago
2009
IEEE
We propose a novel design flow for mismatch and processvariation aware optimization of nanoscale CMOS Active Pixel Sensor (APS) arrays. As a case study, an 8 × 8 APS array is de...
ASPDAC
2009
ACM
14 years 3 months ago
2009
ACM
— Negative Bias Temperature Instability (NBTI) in PMOS transistors has become a major reliability concern in present-day digital circuit design. Further, with the recent usage of...