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» Design space exploration for 3D architectures
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IPPS
2007
IEEE
14 years 3 months ago
Towards Optimal Multi-level Tiling for Stencil Computations
Stencil computations form the performance-critical core of many applications. Tiling and parallelization are two important optimizations to speed up stencil computations. Many til...
Lakshminarayanan Renganarayanan, Manjukumar Harthi...
DAC
2007
ACM
14 years 9 months ago
Parameterized Macromodeling for Analog System-Level Design Exploration
In this paper we propose a novel parameterized macromodeling technique for analog circuits. Unlike traditional macromodels that are only extracted for a small variation space, our...
Jian Wang, Xin Li, Lawrence T. Pileggi
DATE
2008
IEEE
117views Hardware» more  DATE 2008»
14 years 3 months ago
Architecture Exploration of NAND Flash-based Multimedia Card
In this paper, we present an architecture exploration methodology for low-end embedded systems where the reduction of cost is a primary design concern. The architecture exploratio...
Sungchan Kim, Chanik Park, Soonhoi Ha
DATE
2005
IEEE
134views Hardware» more  DATE 2005»
14 years 2 months ago
Assertion-Based Design Exploration of DVS in Network Processor Architectures
With the scaling of technology and higher requirements on performance and functionality, power dissipation is becoming one of the major design considerations in the development of...
Jia Yu, Wei Wu, Xi Chen, Harry Hsieh, Jun Yang 000...
DAC
2008
ACM
13 years 10 months ago
Analog parallelism in ring-based VCOs
The performance advantages in parallel ring-based VCOs are explored. When the number of VCOs is doubled, the parallel VCOs enhance phase noise by 3dB, and the within-chip process-...
Daeik D. Kim, Choongyeun Cho, Jonghae Kim