397 search results - page 22 / 80 » Designing Fast Asynchronous Circuits |
ACSD
2009
IEEE
14 years 3 months ago
2009
IEEE
Asynchronous and latency-insensitive circuits offer a similar form of elasticity that tolerates variations in the delays of communication resources of a system. This flexibility ...
DAC
2004
ACM
14 years 9 months ago
2004
ACM
DDECS
2009
IEEE
14 years 3 months ago
2009
IEEE
—Quasi Delay Insensitive asynchronous logic is a very robust system allowing safe implementations while requiring minimal timing assumptions. Unfortunately the design methodologi...
JUCS
2007
13 years 8 months ago
2007
: The development of processors with full custom technology has some disadvantages, such as the time used to design the processors and the cost of the implementation. In this artic...
ICCAD
1994
IEEE
14 years 23 days ago
1994
IEEE
Abstract - Today's digital design systems are running out of steam, when it comes to meeting the challenges presented by simultaneous switching, power consumption and reliabil...