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» Designing Memory Subsystems Resilient to Process Variations
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ICASSP
2010
IEEE
13 years 7 months ago
Simulating dynamic communication systems using the core functional dataflow model
The latest communication technologies invariably consist of modules with dynamic behavior. There exists a number of design tools for communication system design with their foundat...
Nimish Sane, Chia-Jui Hsu, José Luis Pino, ...
VLSID
2010
IEEE
211views VLSI» more  VLSID 2010»
13 years 11 months ago
A Combined DOE-ILP Based Power and Read Stability Optimization in Nano-CMOS SRAM
A novel design approach for simultaneous power and stability (static noise margin, SNM) optimization of nanoCMOS static random access memory (SRAM) is presented. A 45nm single-end...
Garima Thakral, Saraju P. Mohanty, Dhruva Ghai, Dh...
DAC
2006
ACM
14 years 8 months ago
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source...
Swaroop Ghosh, Saibal Mukhopadhyay, Kee-Jong Kim, ...
VLDB
2002
ACM
143views Database» more  VLDB 2002»
13 years 7 months ago
SQL Memory Management in Oracle9i
Complex database queries require the use of memory-intensive operators like sort and hashjoin. Those operators need memory, also referred to as SQL memory, to process their input ...
Benoît Dageville, Mohamed Zaït
DATE
2010
IEEE
159views Hardware» more  DATE 2010»
14 years 19 days ago
A rapid prototyping system for error-resilient multi-processor systems-on-chip
—Static and dynamic variations, which have negative impact on the reliability of microelectronic systems, increase with smaller CMOS technology. Thus, further downscaling is only...
Matthias May, Norbert Wehn, Abdelmajid Bouajila, J...