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» Diagnosis of Hold Time Defects
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ETS
2011
IEEE
230views Hardware» more  ETS 2011»
12 years 7 months ago
Dynamic Test Set Selection Using Implication-Based On-Chip Diagnosis
—As circuits continue to scale to smaller feature sizes, wearout and latent defects are expected to cause an increasing number of errors in the field. Online error detection tec...
Nuno Alves, Y. Shi, N. Imbriglia, Jennifer Dworak,...
DATE
2008
IEEE
74views Hardware» more  DATE 2008»
14 years 2 months ago
A Design-for-Diagnosis Technique for SRAM Write Drivers
∗ Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, a...
Alexandre Ney, Patrick Girard, Serge Pravossoudovi...
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
14 years 2 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...
ICCD
2007
IEEE
125views Hardware» more  ICCD 2007»
14 years 4 months ago
Low-cost run-time diagnosis of hard delay faults in the functional units of a microprocessor
This paper addresses the run-time diagnosis of delay faults in functional units of microprocessors. Despite the popularity of the stuck-at fault model, it is no longer the only re...
Sule Ozev, Daniel J. Sorin, Mahmut Yilmaz
ETS
2011
IEEE
212views Hardware» more  ETS 2011»
12 years 7 months ago
Structural Test for Graceful Degradation of NoC Switches
Abstract—Networks-on-Chip (NoCs) are implicitly fault tolerant due to their inherent redundancy. They can overcome defective cores, links and switches. As a side effect, yield is...
Atefe Dalirsani, Stefan Holst, Melanie Elm, Hans-J...